// apb_debug_port.sv
module apb_debug_port (
  input  logic        clk, rst_n,
  input  logic [31:0] paddr_i,
  input  logic        psel_i, penable_i, pwrite_i,
  input  logic [31:0] pwdata_i,
  output logic [31:0] prdata_o,
  output logic        pready_o, pslverr_o,

  output logic        mem_req_o,
  output logic        mem_we_o,
  output logic [31:0] mem_addr_o,
  output logic [31:0] mem_wdata_o,
  input  logic [31:0] mem_rdata_i,
  input  logic        mem_ack_i
);
  typedef enum {IDLE, SETUP, ACCESS} apb_state_t;
  apb_state_t state, nstate;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) state <= IDLE;
    else        state <= nstate;

  always_comb begin
    nstate = state;
    case (state)
      IDLE:   if (psel_i && !penable_i) nstate = SETUP;
      SETUP:  if (psel_i &&  penable_i) nstate = ACCESS;
      ACCESS: nstate = IDLE;
    endcase
  end

  assign mem_req_o    = (state == ACCESS);
  assign mem_we_o     = pwrite_i;
  assign mem_addr_o   = paddr_i;
  assign mem_wdata_o  = pwdata_i;
  assign prdata_o     = mem_rdata_i;
  assign pready_o     = mem_ack_i;
  assign pslverr_o    = 1'b0;

endmodule